Inductors are utilized extensively in a variety of integrated circuits. FIGS. 1A and 1B illustrate a top and side view of an inductor 12 with metal shielding 14 underneath on top of a substrate 18. Shielding 14 is added under the inductor 12 to move other circuits farther away from the inductor and also to prevent eddy currents and couplings to external circuits and lines. But even with the shielding 14 underneath the inductor, routing traces nearby (like power lines 16, and signal traces 20) still degrade the performance of the integrated circuit. At the present time, layout engineers use spacing to separate the inductor from the other parts of the integrated circuit or device from another. Engineers don't know ahead of time which device or devices is going to be next to the inductor, so they leave space to make sure the devices are completely separated as much as possible. The spacing can be 40 to 60 microns between devices.
The factor of spacing between devices or circuits is important. At present, layout engineers leave “keep out” areas between devices or circuits. This is to prevent coupling between devices or circuits. It is especially critical because layout engineers do not necessarily know which device or devices may be next to others. The current spacing is between 40 microns to 60 microns. As integrated circuits become smaller this spacing requirements becomes unacceptable.
In addition, even when the inductor is separated from the other parts of the integrated circuit in this manner, there is still the possibility of eddy current and direct coupling from the lossy substrate and metal traces nearby, which may come in from sideways, beneath, or on top. Eddy current, is caused when a magnetic field intersects a conductor.
At present, there is a need for sufficient empty space, both sideways and on top, between the inductor and any other routings. Otherwise, the quality factor of planar inductor suffers from electromagnetic losses due to eddy current and direct coupling from lossy substrate and metal traces nearby. Thus the inductor Q factor has degradation due to compact IC layout.
Accordingly, what is desired is a method to further reduce the spacing between devices, and also to reduce the possibility of eddy current and direct coupling from lossy substrate and metal traces nearby. The present invention addresses such a need.